View SL20T0081_8287629.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

sls system logic semiconductor SL20T0081 81 common x 132 segment stn lcd driver / controller SL20T0081
sls system logic semiconductor SL20T0081 introduction the SL20T0081 is a single - chip graphic dot - matrix liquid crystal display driver & controller that can be co nnected directly to a microprocessor bus. 8 - bit parallel or serial display data sent from the microprocessor is stored in the internal display data ram and the chip generates a liquid crysta l drive signal independent of the micro - processor. the SL20T0081 contains 81x132 bits of display data ram and there is a 1 - to - 1 correspondence between the liquid crystal panel pixels and the internal ram bits, and the device contains 81 common output circuits and 132 segment output circuits, so that a single chip can drive a 81x132 dot display (capable of displaying 8 columns x 5 rows of a 16 x 16 dot font). moreover, the capacity of the display can be extended thr ough the use of master/ slave structures between chips. the chips are able to minimize power consumption because no exte rnal operating clock is necessary for the display data ram read/write operation. furthermore, because each chip is equipped internally with a low - power liquid crystal driver power supply, resistors for liquid crystal driver power v oltage adjustment and a display clock rc oscillator circuit, the SL20T0081 series chips can be used to create the lowest power display sys tem with the fewest components for high performance portable systems. direct display of ram data through the display data ram. ram capacity : 81x132 = 8580 bits features ram bit data : ? 1 ? non - illuminated ? 0 ? illuminated (during normal display) high - speed 8 - bit mpu interface the chip can be connected directly to the both the 80x86 series mpus and the 68000 series mpus. serial interface available (supports write operation only). abundant command functions display data read/write,display on/off, normal/reverse display m ode, page address set, display start line set, column address set, status read, display all point on/off, lcd b ias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, v5 voltage regulation internal resistor ratio set. static drive circuit equipped internally for indicators 1 driver, with 4 kinds of flashing mode duty lcd driver bias maximum display matrix 1/81 1/10 or 1/8 81 x 132 1/65 1/9 or 1/7 65 x 132 1/55 1/8 or 1/6 55 x 132 1/49 1/8 or 1/6 49 x 132 1/33 1/6 or 1/5 33 x 132 overview device specification table 1. duty and bias selection
sls system logic semiconductor SL20T0081 built - in power supply circuit low - power liquid crystal display power supply circuit equipped inter nally. booster circuit (with boost ratios of x2 / x3 / x4 / x5, where t he step - up voltage reference power supply can be input externally). high - accuracy voltage adjustment circuit (thermal gradient - 0. 05%/ o c or external input). lcd driver voltage regulator resistors and voltage followers equ ipped internally. rc oscillator circuit equipped internally (external clock can al so be selected). operating voltage range supply voltage (vdd) : 2.4v ~ 3.6v lcd driver voltage (vlcd) : 4.5v ~ 16.0v low power consumption operating power : 40ua typical (conditions:v dd =3v, x 4 boosting (vci = v dd ), v0 =11v, internal power supply on,display off and normal mode is selected ) standby power : 10ua maximum (during power save [standby] mode) operating temperatures wide range of operating temperatures : - 40 to 85 o c cmos process package type tcp
sls system logic semiconductor SL20T0081 vdd vss v0 v1 v2 v3 v4 cap1+ cap1 - cap2+ cap2 - cap3+ vout vext vr iref ire hpmb seg drivers com drivers power supply circuit display data memory 81 x 132 bits display data read circuit column address decoder row address decoder timing generation & read/write circuit coms oscillation circuit command decoder mpu interface status ce1 ce2 rs rd (e) p68/86 ps wr (r/w) d7 (si) d6 (sck) d5 d4 d2 d1 d3 d0 cls ms disp cl sync frs seg0 seg131 com40 com79 coms cap4+ duty0 duty1 vci fr reset com drivers com0 com39 duty2 blockdiagram
sls system logic semiconductor SL20T0081 (0,0) 282 147 104 103 1 325 283 146 y x figure 1. SL20T0081 pad layout item pad no. size unit x y 8900 3000 - chip size pad pitch 1 - 2, 102 - 103, 147 - 148, 281 - 282 131 2 to10, 94 to 102, 104 to 146, 148 to 281, 283 to 325 60 10 - 11, 93 - 94 90 11 to 41, 45 - 46, 50 to 93 80 41 - 42, 44 - 45, 46 - 47, 49 - 50 110 42 to 44, 47 to 49 120 m bumped pad size (bottom) 2 to 10, 94 to 102, 148 to 281 37 92 104 to 146, 283 to 325 92 37 11 to 41, 45, 46, 50 to 93 57 92 42 to 44, 47 to 49 67 92 1, 103, 147, 282 72 97 all pad bumped pad height 18 table 2. SL20T0081 pad dimensions cog align key coordination ilb align key coordination potting mark coordination 30 m 30 m 30 m 30 m 30 m 30 m 30 m 60 m 30 m 30 m 30 m ( - 4230.0, - 1415.0) (4230.0, - 1430.0) upper left : ( - 4365.0, 1415.0) (4346.0, 1406.0) lower right : (4365.0, - 1415.0) 60 m 72 m pad configuration pad layout figure 2. align key coordination
sls system logic semiconductor SL20T0081 pad center coordinates pad pad pad pad no. name no. name 1 dummy5 -4121 -1411 57 cap1- 540 -1411 2 dummy6 -3990 -1411 58 cap1+ 620 -1411 3 dummy7 -3930 -1411 59 cap1+ 700 -1411 4 dummy8 -3870 -1411 60 cap2+ 780 -1411 5 dummy9 -3810 -1411 61 cap2+ 860 -1411 6 dummy10 -3750 -1411 62 cap2- 940 -1411 7 dummy11 -3690 -1411 63 cap2- 1020 -1411 8 dummy12 -3630 -1411 64 vdd 1100 -1411 9 dummy13 -3570 -1411 65 vext 1180 -1411 10 dummy14 -3510 -1411 66 iref 1260 -1411 11 frs -3420 -1411 67 test_vref 1340 -1411 12 fr -3340 -1411 68 vss 1420 -1411 13 sync -3260 -1411 69 v1 1500 -1411 14 cl -3180 -1411 70 v1 1580 -1411 15 disp -3100 -1411 71 v2 1660 -1411 16 vdd -3020 -1411 72 v2 1740 -1411 17 vss -2940 -1411 73 v3 1820 -1411 18 ce1 -2860 -1411 74 v3 1900 -1411 19 ce2 -2780 -1411 75 v4 1980 -1411 20 vdd -2700 -1411 76 v4 2060 -1411 21 resetb -2620 -1411 77 v0 2140 -1411 22 rs -2540 -1411 78 v0 2220 -1411 23 vss -2460 -1411 79 vr 2300 -1411 24 wr(r/w) -2380 -1411 80 vr 2380 -1411 25 rd(e) -2300 -1411 81 vss 2460 -1411 26 vdd -2220 -1411 82 vss 2540 -1411 27 d<0> -2140 -1411 83 vdd 2620 -1411 28 d<1> -2060 -1411 84 ms 2700 -1411 29 d<2> -1980 -1411 85 cls 2780 -1411 30 d<3> -1900 -1411 86 vss 2860 -1411 31 d<4> -1820 -1411 87 p68/80 2940 -1411 32 d<5> -1740 -1411 88 ps 3020 -1411 33 d<6> -1660 -1411 89 vdd 3100 -1411 34 d<7> -1580 -1411 90 hpmb 3180 -1411 35 vss -1500 -1411 91 vss 3260 -1411 36 vdd -1420 -1411 92 ire 3340 -1411 37 duty0 -1340 -1411 93 vdd 3420 -1411 38 duty1 -1260 -1411 94 trcon 3510 -1411 39 vdd -1180 -1411 95 vss 3570 -1411 40 vss -1100 -1411 96 trim<4> 3630 -1411 41 duty2 -1020 -1411 97 trim<3> 3690 -1411 42 vdd -910 -1411 98 vss 3750 -1411 43 vdd -790 -1411 99 trim<2> 3810 -1411 44 vdd -670 -1411 100 trim<1> 3870 -1411 45 vci -560 -1411 101 vss 3930 -1411 46 vci -480 -1411 102 trim<0> 3990 -1411 47 vss -370 -1411 103 dummy15 4121 -1411 48 vss -250 -1411 104 dummy16 4361 -1250 49 vss -130 -1411 105 com<39> 4361 -1190 50 vout -20 -1411 106 com<38> 4361 -1130 51 vout 60 -1411 107 com<37> 4361 -1070 52 cap4+ 140 -1411 108 com<36> 4361 -1010 53 cap4+ 220 -1411 109 com<35> 4361 -950 54 cap3+ 300 -1411 110 com<34> 4361 -890 55 cap3+ 380 -1411 111 com<33> 4361 -830 56 cap1- 460 -1411 112 com<32> 4361 -770 x y x y
sls system logic semiconductor SL20T0081 pad center coodinates (continued) pad pad pad pad no. name no. name 113 com<31> 4361 -710 169 seg<20> 2730 1411 114 com<30> 4361 -650 170 seg<21> 2670 1411 115 com<29> 4361 -590 171 seg<22> 2610 1411 116 com<28> 4361 -530 172 seg<23> 2550 1411 117 com<27> 4361 -470 173 seg<24> 2490 1411 118 com<26> 4361 -410 174 seg<25> 2430 1411 119 com<25> 4361 -350 175 seg<26> 2370 1411 120 com<24> 4361 -290 176 seg<27> 2310 1411 121 com<23> 4361 -230 177 seg<28> 2250 1411 122 com<22> 4361 -170 178 seg<29> 2190 1411 123 com<21> 4361 -110 179 seg<30> 2130 1411 124 com<20> 4361 -50 180 seg<31> 2070 1411 125 com<19> 4361 10 181 seg<32> 2010 1411 126 com<18> 4361 70 182 seg<33> 1950 1411 127 com<17> 4361 130 183 seg<34> 1890 1411 128 com<16> 4361 190 184 seg<35> 1830 1411 129 com<15> 4361 250 185 seg<36> 1770 1411 130 com<14> 4361 310 186 seg<37> 1710 1411 131 com<13> 4361 370 187 seg<38> 1650 1411 132 com<12> 4361 430 188 seg<39> 1590 1411 133 com<11> 4361 490 189 seg<40> 1530 1411 134 com<10> 4361 550 190 seg<41> 1470 1411 135 com<9> 4361 610 191 seg<42> 1410 1411 136 com<8> 4361 670 192 seg<43> 1350 1411 137 com<7> 4361 730 193 seg<44> 1290 1411 138 com<6> 4361 790 194 seg<45> 1230 1411 139 com<5> 4361 850 195 seg<46> 1170 1411 140 com<4> 4361 910 196 seg<47> 1110 1411 141 com<3> 4361 970 197 seg<48> 1050 1411 142 com<2> 4361 1030 198 seg<49> 990 1411 143 com<1> 4361 1090 199 seg<50> 930 1411 144 com<0> 4361 1150 200 seg<51> 870 1411 145 comsr 4361 1210 201 seg<52> 810 1411 146 dummy17 4361 1270 202 seg<53> 750 1411 147 dummy18 4121 1411 203 seg<54> 690 1411 148 dummy19 3990 1411 204 seg<55> 630 1411 149 seg<0> 3930 1411 205 seg<56> 570 1411 150 seg<1> 3870 1411 206 seg<57> 510 1411 151 seg<2> 3810 1411 207 seg<58> 450 1411 152 seg<3> 3750 1411 208 seg<59> 390 1411 153 seg<4> 3690 1411 209 seg<60> 330 1411 154 seg<5> 3630 1411 210 seg<61> 270 1411 155 seg<6> 3570 1411 211 seg<62> 210 1411 156 seg<7> 3510 1411 212 seg<63> 150 1411 157 seg<8> 3450 1411 213 seg<64> 90 1411 158 seg<9> 3390 1411 214 seg<65> 30 1411 159 seg<10> 3330 1411 215 seg<66> -30 1411 160 seg<11> 3270 1411 216 seg<67> -90 1411 161 seg<12> 3210 1411 217 seg<68> -150 1411 162 seg<13> 3150 1411 218 seg<69> -210 1411 163 seg<14> 3090 1411 219 seg<70> -270 1411 164 seg<15> 3030 1411 220 seg<71> -330 1411 165 seg<16> 2970 1411 221 seg<72> -390 1411 166 seg<17> 2910 1411 222 seg<73> -450 1411 167 seg<18> 2850 1411 223 seg<74> -510 1411 168 seg<19> 2790 1411 224 seg<75> -570 1411 x y x y
sls system logic semiconductor SL20T0081 pad center coodinates (continued) pad pad pad pad no. name no. name 225 seg<76> -630 1411 281 dummy1 -3990 1411 226 seg<77> -690 1411 282 dummy2 -4121 1411 227 seg<78> -750 1411 283 dummy3 -4361 1270 228 seg<79> -810 1411 284 com<40> -4361 1210 229 seg<80> -870 1411 285 com<41> -4361 1150 230 seg<81> -930 1411 286 com<42> -4361 1090 231 seg<82> -990 1411 287 com<43> -4361 1030 232 seg<83> -1050 1411 288 com<44> -4361 970 233 seg<84> -1110 1411 289 com<45> -4361 910 234 seg<85> -1170 1411 290 com<46> -4361 850 235 seg<86> -1230 1411 291 com<47> -4361 790 236 seg<87> -1290 1411 292 com<48> -4361 730 237 seg<88> -1350 1411 293 com<49> -4361 670 238 seg<89> -1410 1411 294 com<50> -4361 610 239 seg<90> -1470 1411 295 com<51> -4361 550 240 seg<91> -1530 1411 296 com<52> -4361 490 241 seg<92> -1590 1411 297 com<53> -4361 430 242 seg<93> -1650 1411 298 com<54> -4361 370 243 seg<94> -1710 1411 299 com<55> -4361 310 244 seg<95> -1770 1411 300 com<56> -4361 250 245 seg<96> -1830 1411 301 com<57> -4361 190 246 seg<97> -1890 1411 302 com<58> -4361 130 247 seg<98> -1950 1411 303 com<59> -4361 70 248 seg<99> -2010 1411 304 com<60> -4361 10 249 seg<100> -2070 1411 305 com<61> -4361 -50 250 seg<101> -2130 1411 306 com<62> -4361 -110 251 seg<102> -2190 1411 307 com<63> -4361 -170 252 seg<103> -2250 1411 308 com<64> -4361 -230 253 seg<104> -2310 1411 309 com<65> -4361 -290 254 seg<105> -2370 1411 310 com<66> -4361 -350 255 seg<106> -2430 1411 311 com<67> -4361 -410 256 seg<107> -2490 1411 312 com<68> -4361 -470 257 seg<108> -2550 1411 313 com<69> -4361 -530 258 seg<109> -2610 1411 314 com<70> -4361 -590 259 seg<110> -2670 1411 315 com<71> -4361 -650 260 seg<111> -2730 1411 316 com<72> -4361 -710 261 seg<112> -2790 1411 317 com<73> -4361 -770 262 seg<113> -2850 1411 318 com<74> -4361 -830 263 seg<114> -2910 1411 319 com<75> -4361 -890 264 seg<115> -2970 1411 320 com<76> -4361 -950 265 seg<116> -3030 1411 321 com<77> -4361 -1010 266 seg<117> -3090 1411 322 com<78> -4361 -1070 267 seg<118> -3150 1411 323 com<79> -4361 -1130 268 seg<119> -3210 1411 324 comsl -4361 -1190 269 seg<120> -3270 1411 325 dummy4 -4361 -1250 270 seg<121> -3330 1411 271 seg<122> -3390 1411 272 seg<123> -3450 1411 273 seg<124> -3510 1411 274 seg<125> -3570 1411 275 seg<126> -3630 1411 276 seg<127> -3690 1411 277 seg<128> -3750 1411 278 seg<129> -3810 1411 279 seg<130> -3870 1411 280 seg<131> -3930 1411 x y x y
sls system logic semiconductor SL20T0081 power supply pins lcd power supply circuit pins pin name i/o function vdd power supply positive power supply. vss power supply system ground. vci power supply voltage booster input pin. the power supply for the voltage boos ter. vci input voltage is the reference of boosted output voltage (vout) of voltage boo ster. v0 v1 v2 v3 v4 power supply lcd driver supply voltage pins. when the internal lcd power supply circuit is enabled, these vol tages are generated by it. when the internal lcd power supply circuit is disabled, these vo ltages must be supplied externally, and they should have the following relationship. vss < v4 < v3 < v2 < v1 < v0 pin description pin name i/o function cap1+ o voltage booster pin. connect a capacitor between this pin and th e cap1 - pin cap1 - o voltage booster pin. connect a capacitor between this pin and th e cap1+ pin cap2+ o voltage booster pin. connect a capacitor between this pin and th e cap2 - pin cap2 - o voltage booster pin. connect a capacitor between this pin and th e cap2+ pin cap3+ o voltage booster pin. (refer the application example to connectin g a capacitor) vout o voltage booster pin. connect a capacitor between this pin and vs s. vext i this is the external reference voltage input pin of the lcd powe r supply circuit. this pin is valid only when internal reference voltage circuit i s disabled (iref=0). cap4+ o voltage booster pin. (refer the application example to connectin g a capacitor) ire i internal voltage regulator resistor enable pin. this pin selects the resistors for the v0 voltage level adjustme nt. ire = 1 : use the internal resistors ire = 0 : do not use the internal resistors. the v0 voltage level is con trolled by the external resisters that connected among v0 pin and vr pin and vss. vr i external v0 voltage adjustment pin. vr pin is valid only when the internal voltage regulator resisto rs are not used (ire=0) iref i internal reference voltage circuit enable pin. iref = 0 : internal reference voltage circuit is disabled. external refer ence voltage is inputted via vext pin. iref = 1 : internal reference voltage circuit is enabled.
sls system logic semiconductor SL20T0081 system control pins pin name i/o function ms i this pin selects the master/slave operation for the SL20T0081 chip. master operation outputs the timing signals that are required for the lcd display , while slave operation inputs the timing signals required for the liquid crystal displa y. ms = 1 : master operation ms = 0 : slave operation following table shows difference of the master operation and the slave operation. ms 1 internal oscillator circuit enabled disabled cls 1 0 0 disabled - internal power supply circuit enabled enabled cl output input sync disp output output output output disabled input input input cl i/o this is the display clock input/output pin. when multiple SL20T0081 chips are used in master/slave mode, all of cl pins must be connected each other. disp i/o this is the liquid crystal display blanking control pin. when multiple SL20T0081 chips are used in master/slave mode, all of disp pins must be connected each other. hpmb i this is the power control pin for the power supply circuit for l iquid crystal drive. hpmb = 1 : normal mode hpmb = 0 : high power mode this pin is enabled only when the master operation mode is selec ted. it is fixed to either 0 or 1 when the slave operation mode is s elected. cls i internal rc oscillator enable pin. cls = 1 : internal oscillator circuit is enabled. cls = 0 : internal oscillator circuit is disabled. when cls=0, the display clock must be inputted through the cl pi n. this pin is valid only when SL20T0081 operating in master operation. sync i/o lcd synchronization signal input/output pin. when multiple SL20T0081 chips are used in master/slave mode, all of sync pins must be connected each other. duty0 duty1 duty2 i the lcd driver duty ratio selection pins. duty1 0 1 duty0 0 1 duty ratio 1/81 1/65 1 0 0 1 1/55 1/49 0 0 1/33 duty2 1 0 0 0 0 1 1 1/81 1 common output normal ? ? ? ? even, odd when duty = (1, 1, 1), 1/81 duty ratio is selected, and common o utput pin configuration is changed. at this mode, all even numbered common output pins are outputting right side of the device and all odd numbered common output pins are outputtin g left side of the device.
sls system logic semiconductor SL20T0081 system interface pins pin name i/o function d7 ~ d0 (si) (sck) i/o 8 bit bi - directional data bus that should be connected to the standard mp u data bus. when ps=0 the serial interface is enabled and pins are set as fo llowing. d7 : serial data input (si) d6 : serial interface clock input (sck) d5 ~ d0 : high impedance state when the chip does not be selected, d7 ~ d0 are set to high impe dance. rs i display data / control data selection signal input pin rs = 1 : d7 ~ d0 input are display data rs = 0 : d7 ~ d0 input are control data reset i device reset pin. when reset = 0, device initialization operation is executed. ce1 ce2 i chip select signal input pins when ce1 = 0 and ce2 = 1, then the chip select becomes active, and data/command i/o is enabled. rd (e) i when the device connected to an 8080 mpu bus, this pin acts as ? active low ? read signal input pin. if the device is selected and rd = 0, then SL20T0081 outputs the data to data bus pins. when the device connected to a 6800 mpu bus, this pin acts as ? active high ? r/w enable signal input pin. if the device is selected and rd = 1, t hen SL20T0081 executes read or write operation that controlled by wr signal. wr (r/w) i when the device connected to an 8080 mpu bus, this pin acts as ? active low ? write signal input pin. if the device is selected and wr = 0, then SL20T0081 accepts the data via data bus pins. when the device connected to a 6800 mpu bus, this pin acts as re ad/write control signal input pin. wr(r/w) = 1 : read wr(r/w) = 0 : write p68/80 i bus type selection pin. p68/80 = 1 : 6800 mpu bus type interface. p68/80 = 0 : 8080 mpu bus type interface ps i parallel data transfer / serial data transfer mode selection pin . ps = 1 : parallel data transfer mode. ps = 0 : serial data transfer mode. when ps = 0, rd(e) and wr(r/w) pins are fixed to either 0 or 1. ps data transfer mode data bus read sck pin write 1 parallel data transfer d7 ~d0 enabled - enabled 0 serial data transfer d7 (si) disabled d6 (sck) enabled
sls system logic semiconductor SL20T0081 liquid crystal drive pins lcd common driver output pins. common driver output voltage is controlled by internal scanning data and fr signal. pin name i/o function seg0 ~ seg131 o lcd segment driver output pins. segment driver output voltage is controlled by display data and fr signal. display data fr segment driver output voltage normal display reverse display 1 0 vss v3 0 0 v3 vss 1 1 v0 v2 0 1 v2 v0 power save vss com0 ~ com79 o coms(r) coms(l) o common drive output for the icons. there are two coms pin, coms( r), coms(l). they output same signal. when in master/slave mode, the same sig nal is output by both master and slave. scan data 1 fr 1 1 0 0 1 0 0 power save mode common driver output voltage vss v0 v1 v4 vss fr o static segment driver output pin. this pin is paired with frs pi n. frs o static segment driver output pin. this pin is paired with fr pin .
sls system logic semiconductor SL20T0081 microprocessor interface chip select input there are ce1 and ce2 pins for chip selection. the SL20T0081 can interface with an mpu only when ce1 is ? l ? and ce2 is ? h ? . when these pins are set to any other combination, rs, rdb(e) a nd_wrb(rw) inputs are disabled and d0to d7 are to be high impedance. and, in case of serial interfa ce, the internal shift register and the counter are reset. parallel / serial interface SL20T0081 has three types of interface with an mpu, which are one serial and two parallel interfaces. this parallel or serial inter face is determined by ps pin. table 3. parallel / serial interface mode parallel interface (ps = ? h ? ) the 8 - bit bi - directional data bus is used in parallel interface and the type of mpu is selected by p68/80 as shown in table 4. the type of data transfer is determined by signals at rs, rd(e) and wr(r/w) as shown in table 5. table 4. microprocessor selection for parallel interface table 5. parallel data transfer function description p68/80 ce1 ce2 rs rd(e) wr(r/w) d0 to d7 mpu bus h ce1 ce2 rs e r/w d0 to d7 6800 - series l ce1 ce2 rs rd wr d0 to d7 8080 - series common 6800 - series 8080 - series rs rd (e) wr (r/w) rd wr description h h h l h h h l h l l l h h h l l h h l display data read out display data write register status read writes to internal register (instruction) ps type ce1 p68/80 interface mode 6800 - series mpu mode l 8080 - series mpu mode ce2 ce1 parallel h l serial ce1 ce2 * x serial - mode ce2 h * x :don ? t care
sls system logic semiconductor SL20T0081 serial interface (ps = ? l ? ) when the SL20T0081 is active, serial data (d7) and serial clock (d6) input are ena bled. and not active,the internal 8 - bit shift register and the 3 - bit counter are reset. serial data can be read on the rising edg e of serial clock going into d6 and processed as 8 - bit parallel data on the eighth serial clock. serial data input is display data when rs is high and caused by the line length, the operation check on the actual machine is recommended. busy flag the busy flag indicates whether the SL20T0081 is operating or not. when d7 is ? h ? in read status operation, this device is in busy status and will accept only read status instru ction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which impr oves the mpu performance. ce1 ce2 sid sclk rs figure 3. serial interface timing d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4
sls system logic semiconductor SL20T0081 data transfer the SL20T0081 used bus holder and internal data bus for data transfer with th e mpu. when writing data from the mpu to internal ram, data is automatically transferred the bus h older to the ram as shown in figure 4. and when reading data from internal ram to the mpu, the data for the init ial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 5. this means that a dummy read cycle must be inserted between each pair of ad dress sets when a sequence of address sets is executed. therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. mpu signals internal signals wr bus holder column address figure 4. write timing n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) n+4 n d(n) d(n+1) d(n+2) d(n+3) rs wr d7 ~ d0
sls system logic semiconductor SL20T0081 mpu signals internal signals bus holder column address figure 5. read timing n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) n+4 n dummy d(n) d(n+1) d(n+2) rs wr d7 ~ d0 rd wr rd
sls system logic semiconductor SL20T0081 lcd display circuit display data ram the display data ram stores pixel data for the lcd. it is 81 - row by 132 - column addressable array. each pixel can be selected when the page and column addresses are specified . the 81 row are divided into 10 pages of 8 lines and the 11th page with a single line (d0 only). data is read fro m or written to the 8 lines of each page directly through d7 to d0. the display data of d7 to d0 from the microprocessor c orrespond to the lcd common lines as shown in figure 6. the microprocessor can read from and write to ram thro ugh the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. page address circuit this circuit is for providing a page address to display data ra m show in figure 6. it incorporates 4 - bit page address register changed by only the ? set page ? instruction. page address 11 is a special ram area for the icon s and display datad0 is only valid. when page address is above 8, it is imposs ible to access to display data ram. line address circuit this circuit assigns display data ram a line address correspond ing to the first line (com0) of the display. therefore, by setting line address repeatedly, it is possible to realize th e screen scrolling and page switching without changing the contents of display data ram as shown in figure 6. it incorp orates 7 - bit line address register changed by only the initial display line instruction and 7 - bit counter circuit. at the beginning of each lcd frame, the co ntents of register are copied to the line counter which is increased by cl signal and g enerates the line address for transferring the 132 - bit ram data to the display data latch circuit. however, display dat a of icons are not scrolled because the mpu can not access line address of icons. 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 db0 db1 db2 db3 db4 com0 com1 com2 com3 com4 display data ram lcd panel figure 6. display data ram to lcd panel data transfer
sls system logic semiconductor SL20T0081 column address circuit column address circuit has an 8 - bit preset counter that provides column address to the display d ata ram as show in figure 7. when set column address msb/lsb instruction is issued, 8 - bit [y7:y0] is updated. and, since this address is increased by 1 each or write data instruction, microprocessor can access the display data continuously. however, the counter is not increased and locked if a non - existing address above 84h. it is unlocked if a column address i s set again by set column address msb/lsb instruction. and the column address counter is independent of page address register. adc select instruction makes it possible to invert the relation ship between the column address and the segment outputs.it is necessary to rewrite the display data on built - in ram after issuing adc select instruction. refer to the following figure 7. segment control circuit this circuit controls the display data by the display on/off, r everse display on/off and entire display on/off instructions without changing the data in display data ram. seg output column address display data seg 0 00 h 1 seg 1 01 h 0 seg 2 02 h 1 seg 3 03 h 1 seg 4 04 h 0 seg 127 7 fh 1 seg 128 80 h 0 seg 129 81 h 0 seg 130 82 h 1 seg 131 83 h 0 adc = 0 adc = 1 lcd panel figure 7. the relationship between column address and segment ou tput
sls system logic semiconductor SL20T0081 d0 d1 d2 d3 d4 d5 d6 d7 page0 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h com0 com1 com2 com3 com4 com5 com6 com7 0 0 0 0 d0 d1 d2 d3 d4 d5 d6 d7 page 1 08 h 09 h 0 ah 0 bh 0 ch 0 dh 0 eh 0 fh 0 0 0 1 d0 d1 d2 d3 d4 d5 d6 d7 page 2 0 0 1 0 d0 d1 d2 d3 d4 d5 d6 d7 page 3 0 0 1 1 d0 d1 d2 d3 d4 d5 d6 d7 page 4 0 1 0 0 d0 d1 d2 d3 d4 d5 d6 d7 page 5 0 1 0 1 d0 d1 d2 d3 d4 d5 d6 d7 page 6 0 1 1 0 d0 d1 d2 d3 d4 d5 d6 d7 page 7 0 1 1 1 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 coms 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1 ah 1 bh 1 ch 1 dh 1 eh 1 fh 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 28 h 29 h 2 ah 2 bh 2 ch 2 dh 2 eh 2 fh 31 h 32 h 33 h 34 h 35 h 36 h 37 h 38 h 39 h 3 ah 3 bh 3 ch 3 dh 3 eh 3 fh 30 h 1 0 1 0 d0 page 10 column address adc=0 adc=1 00 01 02 03 04 05 06 7 d 7 e 7 f 80 81 82 83 ---- 83 82 81 80 7 f 7 e 7 d 06 05 04 03 02 01 00 ---- seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg125 seg126 seg127 seg128 seg129 seg130 seg131 ---- lcd output example of when initial display start line address is 1ch. 1/81 duty d0 d1 d2 d3 d4 d5 d6 d7 page 8 1 0 0 0 40 h 41 h 42 h 43 h 44 h 45 h 46 h 47 h d0 d1 d2 d3 d4 d5 d6 d7 page 9 1 0 0 1 48 h 49 h 4 ah 4 bh 4 ch 4 dh 4 eh 4 fh com64 com65 com66 com67 com68 com69 com70 com71 com72 com73 com74 com75 com76 com77 com78 com79 1/65 duty figure 8. display data ram map (1/81, 1/65 duty mode)
sls system logic semiconductor SL20T0081 oscillator this is completely on - chip oscillator and its frequency is nearly independent of vdd. this oscillator signal is used in the voltage converter and display timing generation circuit. the oscillator circuit is only enabled when ms= ? h ? and cls= ? h ? . when on - chip oscillator is not used, cls pin must be ? l ? condition. in this time, external clock must be input from cl pin. display timing generator circuit this circuit generates some signals to be used for displaying l cd. the display clock, cl generated by oscillation clock, generates a clock to the line counter and a latch signal to the display data latch. the line address of on - chip ram is generated in synchronization with the display clock (cl) and the 132 - bit display data is latched by the display data latch circuit in synchronization with display clock. the di splay data which is read to the lcd driver is completely independent of the access to the display data ram from the micro processor. the lcd ac signal, sync is generated from the display clock. 2 - frame ac driver waveforms with internal timing signal are shown in figure 8. in a multiple chip configuration, the slave chip requires the s ync, cl and disp signals from the master. table 6 shows the sync, cl, and disp status. table 6. master and slave timing signal status operation mode oscillator sync cl disp on(internal clock used) output output output off(external clock used) output input output master slave - input input input
sls system logic semiconductor SL20T0081 common output control circuit this circuit controls the relationship between the number of co mmon output and specified duty ratio. shl select instruction specifies the scanning direction of the common outpu t pins. table 7. the relationship between duty ratio and common output duty shl common output pins coms com 0 ~ 15 com 0 ~ 15 0 1 1/33 1/49 0 1 nc *1 : no connection com 16 ~ 23 com 24 ~ 26 com 27 ~ 31 com 32 ~ 39 com 53 ~ 55 com 56 ~ 63 0 1 1/55 1/65 0 1 1/81 0 1 com 64 ~ 79 com 48 ~ 52 com 16 ~ 31 com 31 ~ 16 com 15 ~ 0 com0 ~ com23 com24 ~ com47 com 0 ~ com79 com 79 ~ com0 com47 ~ com24 com23 ~ com0 com0 ~ com26 com27 ~ com53 com0 ~ com31 com32 ~ com63 com63 ~ com32 nc *1 com31 ~ com0 com53 ~ com27 com26 ~ com0 com 40 ~ 47 coms nc *1 nc *1 nc *1 nc *1 nc *1 nc *1 nc *1
sls system logic semiconductor SL20T0081 power supply circuits the power supply circuits generate the voltage levels necessary to driver liquid crystal driver circuits with low power consumption and the fewest components. there are voltage convert er circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and c ontrolled by power control instruction . for details, refers to ? instruction description ? . table 8 shows the referenced combinations in using power suppl y circuits. table 8. recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/r circuits v/f circuits vout v0 v1 to v4 1 1 1 on on on open open open only the internal power supply circuits are used 0 1 1 off on on external input open open only the voltage regulator circuits and voltage follower circuits are used 0 0 1 off off on external input open open only the voltage follower circuits are used 0 0 0 off off off external input open external input only the external power supply circuits are used
sls system logic semiconductor SL20T0081 figure 9. power supply circuits for various voltage boosting ( a) 2 - times voltage boosting configuration (vout = 2vci) c1 c1 c1 ( b) 3 - times voltage boosting configuration (vout = 3vci) vci vss vout c4+ c3+ c1 - c1+ c2+ c2 - vdd vci c1 c1 c1 c1 vci vss vout c4+ c3+ c1 - c1+ c2+ c2 - vdd vci ( d) 5 - times voltage boosting configuration (vout = 5vci) + + + + + + + c1 c1 vci vss vout c4+ c3+ c1 - c1+ c2+ c2 - vdd vci + + c1 c1 c1 c1 vci vss vout cap4+ cap3+ cap1 - cap1+ cap2+ cap2 - vdd vci c1 + + + + + ( c) 4 - times voltage boosting configuration (vout = 3vci)
sls system logic semiconductor SL20T0081 voltage regulator circuits the function of the internal voltage regulator circuits is to de termine liquid crystal operating voltage, v0,by adjusting resistors, ra and rb, within the range of [v0]< [vout]. because vout is the operating voltage of operational amplifier circuits showing figure 10, it is necessary to be appl ied internally or externally. for the eq. 1, we determine v0 by ra, rb and vev. the ra are co nnected internally or externally by intrs pin. and vev called the voltage of electronic volume is determined by eq. 2,, where the parameter a is the value selected by instruction, ? set reference voltage register ? , within the range 0 to 63. vref voltage at ta = 25 o c is shown in table 9. table 9. vref voltage at ta = 25 o c ref temp. coefficient vref [v] h - 0.05% / o c 2.1 l external input vext table 10. electronic contrast control register (64 steps) vr5 vr4 vr3 vr2 vr1 vr0 reference voltage parameter v0 contrast minimum : : : : : : maximum low : : : : : : high 0 0 0 0 0 0 0 1 : : : : 32( default) : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 0 0 0 0 0 1 : : : : : : : : : : 1 0 0 0 0 0 : : : : : : : : : : : : rb v0 = ( 1 + ) x v ev [v] (eq.1) ra (63 - a ) v ev = ( 1 - ) x v ref [v] (eq.2) 162
sls system logic semiconductor SL20T0081 figure 10. internal voltage regulator circuit vout v0 vr vss gnd + v ev - + - vout rb ra rb ? ra ? internal regulator resistors (ra, rb) external regulator resistors (ra ? , rb ? )
sls system logic semiconductor SL20T0081 in case of using internal resistors, ra and rb (intrs = ? h ? ) when intrs pin is ? h ? , resistor ra is connected internally between vr pin and vss, an d rb is connected between v0 and vr. we determine v0 by two instructions, ? regulator resistor select ? and ? set reference voltage ? . table 11. internal rb/ra ratio depending on 3 - bit data (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.4 r2 r1 r0 1 + ( rb/ra ) the following figure shows v0 voltage measured by adjusting inte rnal regulator resistor ratio (rb/ra) and 6 - bit electronic volume registers for each temperature coefficient at ta = 25 o c. figure 11. electronic volume level 0 8 16 24 3 2 40 48 56 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 v0[v] electronic volume level r 2 r 1 r 0 ( 1 1 1 ) ( 1 1 0 ) ( 1 0 1 ) ( 1 0 0 ) ( 0 1 1 ) ( 0 1 0 ) ( 0 0 1 ) ( 0 0 0 )
sls system logic semiconductor SL20T0081 in case of using external resistors, ra and rb (intrs = ? l ? ) when intrs pin is ? l ? , it is necessary to connect external regulator resistor ra betw een vr and vss, and rb between v0 and vr. example : for the following requirements 1. lcd driver voltage, v0 = 10v 2. 6 - bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. maximum current flowing ra, rb = 1ua from requirement 3 from equations eq.3, 4 and 5 ra @ 1.69 [m w ] rb @ 8.31 [m w ] the following table shows the range of v0 depending on the above requirements. table 12. v0 depending on electronic volume level 0 ? ... 32 ? ... 63 electronic volume level 7.57 ? ... 10.00 ? ... 12.43 v0 rb 10 = ( 1 + ) x v ev [v] (eq.3) ra (63 - 32 ) v ev = ( 1 - ) x 2.1 @ 1.698 [v] (eq.4) 162 10 = 1 [ ua] ( eq.5) ra + rb from eq.1 and eq.2
sls system logic semiconductor SL20T0081 voltage follower circuits vlcd voltage (v0) is resistively divided into four voltage leve ls (v1, v2, v3, v4), and those output impedance are converted by the voltage follower for increasing drive capabilit y. the following table shows the relationship between v1 to v level and each duty ratio. table 13. the relationship between v1 to v4 level and duty ratio high power mode the power supply circuit equipped in the SL20T0081 for lcd drive has very low power consumption (in normal mode: hpmb = ? h ? ). if use for lcd panels with large loads, this low - power power supply may cause display quality to degrade. when this occurs, setting the hpmb pin to ? l ? (high power mode) can improve the quality of the display. moreover, if the quality of display is inadequate even after hig h power mode has been set, then it is necessary to add a liquid crystal drive power supply externally ( vout or v0 or v 1, v2, v3, v4 ). duty ratio duty1 duty0 1 / 55 l h 1 / 65 l h lcd bias v1 v2 v3 v4 1/6 (5/6) x v0 (4/6) x v0 (2/6) x v0 (1/6) x v0 1/8 (7/8) xv0 (6/8) x v0 (2/8) x v0 (1/8) x v0 1/7 (6/7) x v0 (5/7) x v0 (2/7) x v0 (1/7) x v0 1/9 (8/9) x v0 (7/9) x v0 (2/9) x v0 (1/9) x v0 1 / 81 l h l h 1/8 (7/8) x v0 (6/8) x v0 (2/8) x v0 (1/8) x v0 1/10 (9/10) x v0 (8/10) x v0 (2/10) x v0 (1/10) x v0 duty2 l l h h 1 / 33 l h 1 / 49 l h 1/5 (4/5) x v0 (3/5) x v0 (2/5) x v0 (1/5) x v0 1/6 (5/6) xv0 (5/6) x v0 (2/6) x v0 (1/6) x v0 l l 1/6 (5/6) x v0 (4/6) x v0 (2/6) x v0 (1/6) x v0 1/8 (7/8) xv0 (6/8) x v0 (2/8) x v0 (1/8) x v0
sls system logic semiconductor SL20T0081 reset circuit setting reset to ? l ? or reset instruction con internal function. when reset becomes ? l ? , following procedure is occurred. display on/off: off all segments on/off: off(normal) adc select: off(normal) reverse display on/off: off(normal) power control register (vc, vr, vf) = (0,0,0) serial interface internal register data clear lcd bias ratio: 1/9 (1/65 duty), 1/8 (1/55 duty), 1/6 (1/33 duty ) on - chip oscillator off power save release read - modify - write: off shl select: off(normal) static indicator mode: off static indicator register: (s1, s0) = (0, 0) display start line: 0 (first) column address: 0 page address: 0 regulator resistor select register: (r2, r1, r0) = (1, 0, 0) reference voltage set: off reference voltage control register: (vr5, vr4, vr3, vr2, vr1, vr 0) = (1, 0, 0, 0, 0, 0) test mode release when reset instruction is issued, following procedure is occurr ed. read - modify - write: off static indicator mode: off static indicator register:(s1, s0) = (0, 0) shl select: 0 display start line: 0 (first) column address: 0 page address: 0 regulator resistor select register: (r2, r1, r0) = (1, 0, 0) reference voltage control register: (vr5, vr4, vr3, vr2, vr1, vr 0) = (1, 0, 0, 0, 0, 0) test mode release while reset is ? l ? or reset instruction is executed,no instruction except read sta tus could be accepted. reset status appears at d4. after d4 becomes ? l ? , any instruction can be accepted. reset must be connected to th e reset pin of the mpu, and initialize the mpu and this lsi at the same time. t he initialization by reset is essential before used.
sls system logic semiconductor SL20T0081 instruction description table 14. instruction table instruction instruction code rs rd wr 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 0 1 1 1 don display on/off function don = 1 : lcd display on don = 0 : lcd display off 0 1 0 0 1 sl5 sl4 sl3 sl2 sl1 sl0 display start line set set the display data ram address that corresponds com0 output 0 1 0 1 0 1 1 p3 p2 p1 p0 set page address set the page address 0 1 0 0 0 0 1 a7 a6 a5 a4 set column address msb set the column address msb 0 1 0 0 0 0 0 a3 a2 a1 a0 set column address lsb set the column address lsb 0 0 1 busy adc onoff reset 0 0 0 0 read status read device internal status 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write display data write data into display ram 0 1 0 1 0 1 0 0 0 0 adc adc set set seg output direction adc = 0 : seg0 seg131 adc = 1 : seg131 seg0 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 read display data read data from display ram 0 1 0 1 0 1 0 0 1 1 rev reverse display on/off set display mode rev = 0 : normal display rev = 1 : reverse display 0 1 0 1 0 1 0 0 1 0 aon all segments on/off set display mode aon = 0 : normal display aon = 1 : display all segments on 0 1 0 1 0 1 0 0 0 1 bias lcd bias select select lcd bias 0 1 0 1 1 1 0 0 0 0 0 set read - modify - write (rmw) mode read - modify - write mode enable 0 1 0 1 1 1 0 1 1 1 0 clear read - modify - write (rmw) mode read - modify - write mode disable 0 1 0 1 1 1 0 0 0 1 0 reset initialize the device 0 1 0 1 1 0 0 cod x x x common output direction (cod) set set com output direction cod = 0 : com0 com63 cod = 1 : com63 com0 0 1 0 0 0 1 0 1 be re fe lcd power setup be : voltage booster enable re : voltage regulator enable fe : voltage follower enable 0 0 1 1 0 0 1 x 0 sl6 1 sl5 0 sl4 1 sl3 0 sl2 0 sl1 1 sl0 display start line set (double byte instruction) set the display data ram address that corresponds com0 output for 1/81 duty (7bits). 0 1 0 1 0 1 0 1 0 0 0 display start line reset reset the display start line. 0 0 1 1 0 0 1 x 0 x 1 x 0 nl4 1 nl3 0 nl2 1 nl1 1 nl0 n - line inversion (double byte instruction) set the display data ram address that corresponds com0 output for 1/81 duty (7bits). 0 1 0 1 0 1 0 1 0 1 0 n - line inversion reset reset the n - line inversion. (n - line inversion disable) x:don ? t care
sls system logic semiconductor SL20T0081 x:don ? t care instruction instruction code rs rd wr 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 0 0 0 0 1 nop function non - operation command 0 1 0 1 1 1 1 x x x x test don ? t use this instruction 0 1 0 1 0 0 1 x x x x test don ? t use this instruction 0 0 1 1 0 0 1 x 0 x 1 x 0 x 1 x 1 x 0 s1 1 s0 static segment driver on (double byte instruction) the static segment driver (fr - frs) is enabled and display mode is controlled by 2 ? nd byte. 0 1 0 1 0 1 0 1 1 0 0 static segment driver off the static segment driver is disabled power save control (compound instruction) the device is entered power saving state when instructions set display off and all segments on. 0 1 0 0 0 1 0 0 r2 r1 r0 voltage regulator resistor ratio set select internal resistor ratio of the voltage regulator (rb/ra) 0 0 1 1 0 0 1 x 0 x 0 vr5 0 vr4 0 vr3 0 vr2 0 vr1 1 vr0 reference voltage register set (double byte instruction) select reference voltage to control display contrast. table 15. instruction table (continued)
sls system logic semiconductor SL20T0081 don =1 : display on don =0 : display off rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 1 0 1 1 1 don display start line set sets the line address of display ram to determine the initial d isplay line. the ram display data is displayed at the top row (com0 when shl = l, com63 when shl = h) of lcd panel. rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 st5 st4 st3 st2 st1 st0 st5 st4 st3 st2 st1 st0 line address 0 1 : 62 0 0 0 0 0 0 0 0 0 0 0 1 : : : : : : 1 1 1 1 1 0 63 1 1 1 1 1 1 set page address sets the page address of display data ram from the microprocess or into the page address register. any ram data bit can be accessed when its page address and column address are specified. along with the column address, the page address defines the address of the display ram to write or read display data. changing the page address doesn ? t effect to display status. rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 1 1 p3 p2 p1 p1 p3 p2 p1 p0 page 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 display on/off turns the display on/off
sls system logic semiconductor SL20T0081 set column address sets the column address of display ram from the microprocessor into column address register. along with the column address, the column address defines the address of the di splay ram to write or read display data. when the microprocessor reads or writes display data to or from display r am, column addresses are automatically increased. rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 a7 a6 a5 a4 rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131 read status read the internal status of the SL20T0081 . set column address msb set column address lsb rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 1 busy adc on/off reset 0 0 0 0 flag description the device is busy when internal operation or reset. any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being busy busy indicates the relationship between ram column address and segmen t driver. 0: reverse direction (seg131 sego ), 1: normal direction (sego seg131 ) adc on/off reset indicates display on / off status. 0: display on, 1: display off indicates the initialization is progress by reset signal. 0: chip is active, 1: chip is being reset
sls system logic semiconductor SL20T0081 write display data 8 - bit data of display data from the microprocessor can be written to the ram location specified by the column address and page address. the column address is increased by 1 automatic ally so that the microprocessor can continuously write data to the addressed page. rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 write data set page address set column address data read column address is increased automatically after read or write operation. data read continue? optional status no figure 12. sequence for writing display data figure 13. sequence for reading display data read display data 8 - bit data from display data ram specified by the column address a nd page address can be read by this instruction. as the column address is increased by 1 automatically after eac h this instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display data cannot be read through the serial interface. rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 1 read data adc select (segment driver direction select) changes the relationship between ram column address and segment driver. the direction of segment driver output pins can be reversed by software. this makes ic layout flexible in lcd module assembly. adc = 0: normal direction (seg0 seg131 ) adc = 1: reverse direction (seg131 seg0 ) rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 adc 1 1 dummy data read yes set page address set column address data write data read continue? optional status no yes
sls system logic semiconductor SL20T0081 rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ? 1 ? ram bit data = ? 0 ? 0 ( normal) lcd pixel is illuminated lcd pixel is not illuminated 1 ( reverse) lcd pixel is not illuminated lcd pixel is illuminated rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 1 0 0 1 0 eon eon = 0: normal display eon = 1: entire display on select lcd bias selects lcd bias ratio of the voltage required for driving the l cd. set read - modify - write this instruction stops the automatic increment of the column ad dress by the read display data instruction,but the column address is still increased by the write display data inst ruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the reset modify - read instruction. rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 1 1 0 0 0 0 0 reverse display on / off reverses the display status in lcd panel without rewriting the contents of the display data ram. all segments on / off forces the whole lcd points to be turned on regardless of the co ntents of the display data ram.at this time, the contents of the display data ram are held. this instruction has priority over the reverse display on / off instruction. rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 1 0 0 0 1 bias lcd bias bias = 0 duty0 duty1 duty ratio bias = 1 1/33 0 0 1/6 1/5 1/49 0 1 1/8 1/6 1/55 1 0 1/8 1/6 1/65 1 1 1/9 1/7 1/81 0 0 1/10 1/8 duty2 0 0 0 0 1
sls system logic semiconductor SL20T0081 reset read - modify - write this instruction cancels the read - modify - write mode, and makes the column address return to its initial v alue just before the set read - modify - write instruction is started. rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 1 1 0 1 1 1 0 set page address set column address (n) dummy read data read set modify - read data write chang complete? reset modify - read return column address no yes data process figure 14. sequence for cursor display rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 1 1 0 0 0 1 0 reset this instruction resets initial display line, column address, pa ge address, and common output status select to their initial status, but does not affect the contents of display data ram. this instruction cannot initialize the lcd power supply, which is initialized by the reset pin.
sls system logic semiconductor SL20T0081 common output direction (cod) set com output scanning direction is selected by this instruction w hich determines the lcd driver output status. rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 1 0 0 shl x x x cod = 0: normal direction ( com0 com79 ) cod = 1: reverse direction ( com79 com0 ) power control selects one of eight power circuit functions by using 3 - bit register. an external power supply and part of internal powe r supply functions can be used simultaneously. x: don ? t care rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 0 1 0 1 internal voltage converter circuit is off internal voltage converter circuit is on internal voltage converter circuit is off internal voltage converter circuit is on internal voltage converter circuit is off internal voltage converter circuit is on regulator resistor select selects resistance ratio of the internal resistor used in the i nternal voltage regulator. see voltage regulator section in power supply circuit. refer to the table 15. rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 (1+ rb / ra) ratio 3.0 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 3.5 4.0 4.5 5.0 ( default) 5.5 6.0 6.4
sls system logic semiconductor SL20T0081 reference voltage select consists of 2 - byte instruction. the 1 st instruction set reference voltage mode, the 2 nd one updates the contents of reference voltage register. after second instruction, reference voltage mode is released. rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction : set reference voltage register rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 x x vr5 vr4 vr3 vr2 vr0 vr1 vr5 vr4 vr3 vr2 vr0 vr1 reference voltage parameter( a ) v0 contrast 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 0 0 0 0 0 32 ( default) 1 1 1 1 1 0 62 1 1 1 1 1 1 63 : : : : : : : : : : : : : : minimum : : : : : maximum low : : : : : high figure 15. sequence for setting the reference voltage setting reference voltage start 1 st instruction for mode setting 2 nd instruction for register setting setting reference voltage start the 1 st instruction : set reference voltage select mode
sls system logic semiconductor SL20T0081 set static indicator state consists of two bytes instruction. the first byte instruction ( set static indicator mode) enables the second byte instruction (set static indicator register) to be valid. the fir st byte sets the static indicator on /off. when it is on, the second byte updates the contents of static indicator register wi thout issuing any other instruction and this static indicator state is released after setting the data of indicator register. rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 1 0 1 1 0 sm the 2 nd instruction : set static indicator register rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 x x x x x x s0 s1 the 1 st instruction : set static indicator mode (on/off) sm = 0: static instruction off sm = 1: static instruction on s0 s1 status of static indicator output 0 0 off 1 0 on (about 1 second blinking) 1 0 on (about 0.5 second blinking) 1 1 on (always on) nop non operation instruction rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 1 1 0 0 0 1 1 test instruction (test instruction_1 &test instruction_2) thee are the instruction for ic chip testing. please do not use it. if the test instruction is used by accident,it can be cleared by applying ? 0 ? signal to the reset input pin or the reset instruction. rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 1 1 1 x x x x 0 0 1 0 0 1 x x x x
sls system logic semiconductor SL20T0081 power save (compound instruction) if the entire display on/off instruction is issued during the di splay off state, SL20T0081 enters the power save status to reduce the power consumption to the static power consu mption value. according to the status of static indicator mode, power save is entered to one mode of sleep and s tandby mode. when static indicator mode is on, standby mode is issued. when off, sleep mode is issued. power sa ve mode is released by the entire display off instruction. figure 16. power save (compound instruction) - sleep mode this stops all operations in the lcd display system, and as lon g as there are no access from the mpu, the consumption current is reduced to a value near the static curren t. the internal modes are as follows : a. the oscillator circuit and lcd power supply circuit are halted. b. all liquid crystal drive circuit are halted, and the segment in common drive outputs a vss level. - standby mode the duty lcd display system operation are halted and only the s tatic drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. a. the lcd power supply circuits are halted. the oscillator circuit continues to operate. b. the duty drive system liquid crystal drive circuits are halted a nd the segment and common driver outputs a vss level. the static drive system does not operate. when a reset command is performed while in standby mode, the system enter sleep mode. static indicator off static indicator on power save (compound indicator) [display off] [all segments on] sleep mode [oscillator circuit: off] [all com/seg outputs: vss] [consumption current:<2ua] standby mode [oscillator circuit: off [lcd power supply circuit: off] [all com/seg outputs: vss] [consumption current: <10ua] power save off (compound instruction) [all segments off] [static indicator on] 2 bytes command power save off [all segments off] release sleep mode release standby mode
sls system logic semiconductor SL20T0081 referential instruction setup flow (1) user system setup by external pins reset pin = ? h ? waiting for stabilizing waiting for stabilizing the power power on (vdd - vss) keeping the reset pin = ? l ? start of initialization user application setup by internal instructions [adc select] [shl select] [lcd bias select] user lcd power setup by internal instructions [voltage regulator on] user lcd power setup by internal instructions [voltage converter on] user lcd power setup by internal instructions [voltage follower on] user lcd power setup by internal instructions [regulator resistor select] [reference voltage register set] end of initialization figure 17. initializing with the built - in power supply circuits waiting for > 1ms waiting for > 1ms
sls system logic semiconductor SL20T0081 user application setup by internal instructions [adc select] [shl select] [lcd bias select] user lcd power setup by internal instructions [regulator resistor select] [reference voltage register set] set power save release power save referential instruction setup flow (2) end of initialization figure 18. initializing without the built - in power supply circuits user system setup by external pins reset pin = ? h ? waiting for stabilizing the power power on (vdd - vss) keeping the reset pin = ? l ? start of initialization waiting for stabilizing
sls system logic semiconductor SL20T0081 display data ram addressing by instruction [initial display line] [set page address] [set column address] write display on/off by instruction [display on/off] turn display on/off by instruction [display on/off] figure 19. data display setup referential instruction setup flow (3) end of initialization end of display setup
sls system logic semiconductor SL20T0081 turn display on/off by instruction [display off] user lcd power setup by internal instructions [voltage regulator off] user lcd power setup by internal instructions [voltage follower off] waiting for > 50ms user lcd power setup by internal instructions [voltage converter off] waiting for > 1ms waiting for > 1ms power off (vdd - vss) figure 20. power off referential instruction setup flow (4) optional status
sls system logic semiconductor SL20T0081 parameter power supply voltage with triple step - up with quad step - up power supply voltage(3) power supply voltage(4) input voltage output voltage operating temperature storage temperature tcp bare chip symbol vdd v0, vout v1, v2, v3, v4 vin top tst power supply voltage vo conditions - 0.3 ~ +7.0 - 0.3 ~ +7.0 - 0.3 ~ +6.0 - 0.3 ~ +4.5 - 0.3 ~ +18.0 - 0.3 ~ v0 - 0.3 ~ vdd + 0.3 - 40 ~ + 85 - 55 ~ + 100 - 55 ~ + 125 - 0.3 ~ vdd + 0.3 unit v v v v v o c o c v vdd vss vcc gnd v0, vout v1 ~ v4 system (mpu)side SL20T0081 side figure 21. relations between powers and v voltages unless otherwise noted, vss = 0v absolute maximum ratings specifications notes : 1. vdd and vlcd are based on vss = 0v. 2. voltages v0 > v1 > v2 > v3 > v4 > vss must always be satisfied. (vlcd = v0 - vss) 3. if supply voltage exceeds its absolute maximum range,this lsi ma y be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability m ay result. table 16. absolute maximum ratings
sls system logic semiconductor SL20T0081 unless otherwise specified, vss = 0v, vdd = 3.0 v 10%, ta = - 40 to 85 o c dc characteristics item operating voltage symbol vdd condition condition 2.4 - 5.5 min. typ. max. v units vdd pin high - level input voltage vih vin = vdd or vss lcd driver output on resistance ron ta = 25 o c v0 = 8v oscillator frequency internal oscillator fosc 1/81 duty, ta = 25 o c 6.3 low - level input voltage vil 0.8 vdd - vdd v 0 - 0.2 x vdd v high - level output voltage voh low - level output voltage vol ioh = - 0.5ma iol = 0.5ma 0.8 vdd - vdd v 0 - 0.2 x vdd v input leakage current iil - 1.0 - 1.0 ua output leakage current iol - 3.0 - 3.0 ua - 2.0 3.0 k w lcd drive pins 12.6 18.9 khz external input fcl - 12.6 - khz cl operating voltage(2) v0 4.5 - 15.0 v v0 internal oscillator fosc 1/65 duty, ta = 25 o c 5.5 10.9 16.4 khz external input fcl - 10.9 - khz cl internal oscillator fosc 1/55 duty, ta = 25 o c 5 10.0 15.0 khz external input fcl - 10.0 - khz cl internal oscillator fosc 1/49 duty, ta = 25 o c 4.3 8.7 13.0 khz external input fcl - 8.7 - khz cl internal oscillator fosc 1/33 duty, ta = 25 o c 2.9 5.8 8.7 khz external input fcl - 5.8 - khz cl table 17. dc characteristics
sls system logic semiconductor SL20T0081 ( vss = 0v, vdd =2.4 to 3.6v, ta = - 40 to 85 o c) table 18. dc characteristics (continued) x2 - 2.4 3.6 x3 - 2.4 3.6 x4 - 2.4 3.6 v x5 - 2.4 3.2 v v voltage converter input voltage voltage converter output voltage vout x2 /x3 /x4 /x5 voltage conversion (no - load) 95 99 - % vout voltage regulator operating voltage vout 6.0 16.0 - v vout voltage regulator operating voltage v0 4.5 15.0 - v v0 *9 reference voltage vref 2.1 2.16 v ta =25 o c ( - 0. 05%/ o c) 2.04 item symbol condition condition min. typ. max. units pin
sls system logic semiconductor SL20T0081 table 19. dynamic current consumption (1) when the built - in power circuit is off (at operate mode) item symbol condition min. typ. max. unit pin used dynamic current consumption(1) i dd1 vdd =3.0v v0 - vss =11.0v 1/65 duty ratio display pattern off - 15 23 a * 11 ( ta =25 o c) table 20. dynamic current consumption (2) when the built - in power circuit is on (at operate mode) pin used ( ta =25 o c) *12 *12 item symbol condition min. typ. max. unit i dd2 v dd =3.0v (v =v dd, 4 time boosting) v0 - v ss =11.0v, 1/65 duty ratio, display pattern off, normal power mode - 40 60 a v dd =3.0v (v =v dd, 4 time boosting) v0 - v ss =11.0v, 1/65 duty ratio, display pattern checker, normal power mode - 150 200 a dynamic current consumption(2) table 21. current consumption during power save mode ( ta =25 o c) item symbol condition min. typ. max. unit pin used sleep mode current i dd1 during sleep - - 2.0 a standby mode current i dd2 during standby - - 10.0 a
sls system logic semiconductor SL20T0081 table 22. the relationship between oscillation frequency and fr ame frequency [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a sp ike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is applied. *3 . ce1, ce2, rs, d7, to d0, rd(e), wr(r/w), reset, ms, p68/80, ps, intrs, hpmb, cls, cl, sync, fr, disp pins. *4 . d0 to d7, sync, fr, disp, cl pins. *5 . ce1, ce2, rs, d7 to d0, rd(e), wr(r/w), reset, ms, p68/80, ps, i ntrs, hpmb,cls, cl, sync, fr, disp pins. *6 . applies when the db[7:0], sync, fr, disp, and cl pins are in hig h impedance. *7 . resistance value when ? 0. 1[ ma ] is applied during the on status of the output pin segn or comn. ron = v / 0.1 [k ? ] ( v : voltage change when ? 0.1 [ ma ] is applied in the in status.) *8 . see table 22 for the relationship between oscillation frequency and frame fr ame frequency. *9 . the voltage regulator circuit adjusts v0 within the voltage foll ower operating voltage range *10 . on - chip reference voltage source of the voltage regulator circuit t o adjust v0. *11,*12 . applies to the case where the on - chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built - in power supply circuit is on or off. the current flowing throug h voltage regulation resistors (ra and rb) is not included. it does not in clude the current of the lcd panel capacity, wiring capacity, etc. ( fosc:oscillation frequency, f cl : display clock frequency, f fr : lcd ac signal frequency) duty ratio item f cl f fr on - chip oscillator circuit is used f osc 2 x 2 x 81 on - chip oscillator circuit is not used external input ( f cl ) 1/81 f cl 2 x 2 x 81 on - chip oscillator circuit is used f osc 2 x 2 x 65 on - chip oscillator circuit is not used 1/65 f cl 2 x 2 x 65 f osc = 12.57 khz external input ( f cl ) f osc = 10.90 khz on - chip oscillator circuit is used f osc 2 x 2 x 55 on - chip oscillator circuit is not used 1/55 f cl 2 x 2 x 55 external input ( f cl ) f osc = 9.96 khz on - chip oscillator circuit is used f osc 2 x 2 x 49 on - chip oscillator circuit is not used 1/49 f cl 2 x 2 x 49 external input ( f cl ) f osc = 8.72 khz on - chip oscillator circuit is used f osc 2 x 2 x 33 on - chip oscillator circuit is not used 1/33 f cl 2 x 2 x 33 external input ( f cl ) f osc = 5.82 khz
sls system logic semiconductor SL20T0081 ac characteristics ( v dd = 2.4 to 3.6v, ta = - 40 to +85 o c) figure 22. read/write characteristics (8080 - series microprocessor) 0 0 300 60 60 40 15 - 10 item signal symbol min. typ. max. unit remark address setup time address hold time rs t as t ah system cycle time rs t cy pulse width (r) e(rdb) t rd pulse width (w) e(rdb) t wr t ds t dh t acc t od d7 to d0 data setup time data hold time read access time output disable time ns ns ns ns ns ns cl = 100pf - - - - - - - - - - - 140 100 ce1 (ce2 = 1) rs rd, wr d7 ~ d0 (write) d7 ~ d0 (read) t as t ah t cy t pw(r), t pw(w) t dh t ds t acc t od 0.9 vdd 0.1 vdd table 23. read/write characteristics (8080 - series microprocessor)
sls system logic semiconductor SL20T0081 figure 23. read/write characteristics (6800 - series microprocessor) ( vdd = 2.4 to 3.6v, ta = - 40 to +85 o c) item signal symbol min. typ. max. unit remark address setup time address hold time rs t as t ah 0 0 ns system cycle time rs t cy 300 ns pulse width (r) e(rdb) t rd 120 ns pulse width (w) e(rdb) t wr 60 ns t ds t dh 40 15 ns t acc t od - 10 ns cl = 100pf d7 to d0 data setup time data hold time read access time output disable time - - - - - - - - - - - 140 100 ce1 (ce2 = 1) rs e d7 ~ d0 (write) d7 ~ d0 (read) t as t ah t cy t pw(r), t pw(w) t dh t ds t acc t od 0.9 vdd 0.1 vdd table 24. read/write characteristics (6800 - series microprocessor)
sls system logic semiconductor SL20T0081 ( vdd = 2.4 to 3.6v, ta = - 40 to +85 o c) figure 24. serial interface characteristics t css t chs t ass t ahs t cys t wls t whs t dss t dhs 0.1 vdd 0.9 vdd ce1 (ce2 = 1) rs d6 (sck) d7 (si) serial clock cycle sclk high pulse width sclk low pulse width d6 (sclk) t cys t whs twls 250 100 100 - - - address setup time address hold time rs t ass t ahs 150 150 t dss t dhs 100 100 d7 (sid) data setup time data hold time t css t chs 150 150 ce1 ce1 setup time ce1 hold time - - - - - - ns ns ns ns item signal symbol min. typ. max. unit remark table 25. serial interface characteristics
sls system logic semiconductor SL20T0081 ( vdd = 2.4 to 3.6v, ta = - 40 to +85 o c) ( vdd = 2.4 to 3.6v, ta = - 40 to +85 o c) item signal symbol min. typ. max. unit remark fr delay time fr t dfr - 20 80 ns cl=50pf figure 25. reset input timing figure 26. display control output timing reset internal reset operation t resetb t irst item signal symbol min. typ. max. unit remark reset low pulse width reset t resetb 30.0 - - ns reset time - t irst - - 60.0 ns cl fr t dfr table 26. reset input timing table 27. display control output timing
sls system logic semiconductor SL20T0081 reference applications ms ire vci vss vout c4+ c3+ c1 - c1+ c2+ c2 - vr v0 v1 v2 v3 v4 vdd + - c2 c1 c1 c1 c1 + - c2 + - c2 + - c2 + - c2 example 1 : when using internal lcd power circuit (4 - time voltage boost / vci = vdd) ( a) using internal voltage regulator resistors (ire=1) ms ire vci vss vout c4+ c3+ c1 - c1+ c2+ c2 - vr v0 v1 v2 v3 v4 vdd + - c2 c1 c1 c1 c1 + - c2 + - c2 + - c2 + - c2 ( b) using external voltage regulator resistors (ire=0) ra rb ms ire vci vout c4+ c3+ c1 - c1+ c2+ c2 - vr v0 v1 v2 v3 v4 vdd + - c2 + - c2 + - c2 + - c2 + - c2 example 2 : using internal lcd power circuit (not using voltage booster ci rcuit) ms ire vci vout c4+ c3+ c1 - c1+ c2+ c2 - vr v0 v1 v2 v3 v4 vdd + - c2 + - c2 + - c2 + - c2 + - c2 ( d) using external voltage regulator resistors (ire=0) ra rb external power supply external power supply lcd power supply configuration ( c) using internal voltage regulator resistors (ire=1) vss vss vss vss vss vss
sls system logic semiconductor SL20T0081 ms ire vci vss vout c4+ c3+ c1 - c1+ c2+ c2 - vr v0 v1 v2 v3 v4 vdd + - c2 + - c2 + - c2 + - c2 + - c2 example 3 : using internal lcd power circuit (only use voltage follower ci rcuit) ms ire vci vout c4+ c3+ c1 - c1+ c2+ c2 - vr v0 v1 v2 v3 v4 vdd example 4 : using external lcd power supply external power supply external power supply
sls system logic semiconductor SL20T0081 data transfer interface 6800 series mpu ce1 ce2 rs e rw d7~d0 reset vdd vdd ce1 ce2 rs rd(e) wr(r/w) d7~d0 reset p68/80 ps SL20T0081 ( a) 6800 bus type interface 8080 series mpu ce1 ce2 rs rd wr d7~d0 reset vss vdd ce1 ce2 rs rd(e) wr(r/w) d7~d0 reset p68/80 ps SL20T0081 ( b) 8080 bus type interface mpu ce1 ce2 rs si sck reset vdd or vss vss ce1 ce2 rs d7 d6 d5~d0 reset p68/80 ps SL20T0081 ( c) serial interface figure 27. data transfer interface

▲Up To Search▲

Price & Availability of SL20T0081

	To Download SL20T0081 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .